1. Field of the Invention
The present invention is related to hierarchical memory systems, and more particularly to a memory interface that couples a spiral cache memory to other members of a memory hierarchy.
2. Description of Related Art
A spiral cache memory as described in the above-referenced Parent U.S. Patent application supports multiple in-flight requests referencing the same or different values by their address. In order to integrate a spiral cache memory in a hierarchical memory system, while permitting the next lower-order level of the memory hierarchy or a processor to access the same value repeatedly before a request for the same value is completed, a way to ensure that writes to the value are satisfied before subsequent reads is needed. It is desirable to do so without constraining the activity of the processor or lower-order level of the memory hierarchy that is coupled to the front-most storage tile, as to do so would introduce performance penalties, or require the processor architecture and/or program code to constrain the order of accesses. Also, in particular because the backing store will generally have a much higher latency that the spiral cache itself, queues as described in the above-incorporated parent U.S. patent application are needed between the memory hierarchy levels, and in order to not constrain the activity of the spiral cache with respect to the backing store, at least at the internal level of the storage tiles, it is desirable to provide a mechanism to coordinate requests to the backing store so that push-back write values can be coordinated with read requests issued to the backing store. Further, read requests issued to the backing store return values from the backing store into the spiral cache. Without checking the address of each value and tracking all of the values present in the spiral cache, multiple copies of the same value could be read into the spiral cache. Therefore, a mechanism to prevent multiple copies of the same value being returned to the spiral cache is needed.
Therefore, it would be desirable to provide a spiral cache interface to a memory hierarchy and an integrated memory hierarchy including a spiral cache, in which multiple outstanding requests for the same value can be issued into the spiral cache without constraining the processor, program code, or lower-order level of the memory hierarchy. It would further be desirable to provide an interface from the spiral cache to a backing store without constraining the behavior of the network of tiles in the spiral cache or having multiple copies of the same value returned to the spiral cache.